Courses/Computer Science/CPSC 457.F2013/Lecture Notes/SysArch

System Architecture

This session will briefly consider a typical hardware environment that an OS is responsible for managing, with a focus on the x86 platform.

Agenda

HW1 released. Working on defining HW2, HW3, and test1.

Sorry for the svn and VirtualBox image weirdness.

NB: Start with an overview of LXR and the source rpm and tarball in the course VM to finish off the "What is an OS?" discussion. redraw picture, motivate interrupts and exceptions.

We also note that, as the textbook says, OSs started out by replacing the human operator: which is one reason we emphasize part of the definition of an OS as something that loads and prepares software for execution. Main issue: how can the OS simultaneously time-multiplex the CPU(s) for all those processes? But there is another aspect, since sharing the CPU does not imply protection / isolation: space multiplexing memory and the isolation / protection implied.

Start with gdb on our silly programs, hello or addi. observe machine state (i.e., registers)

Focus Questions

• How does a program become a process (cont.)?
• How do low-level hardware primitives enable the higher-level resource management and isolation guarantees of an Operating System kernel?

Notes

• http://www.cpsc.ucalgary.ca/~locasto/teaching/2013/CPSC457-Fall/talks/sysarch.pdf

• Hardware support for protection
  • x86 CPU core architecture, data path, assembly language
  • DPL bits in segment descriptors help label memory pages as belonging to a particular privilege "ring"
• System Architecture Environment and assembly programming (x86 legacy)
  • GDT and IDT
  • http://www.phrack.com/issues.html?issue=59&id=4&mode=txt

• examine process creation via fork(2)

Scribe Notes

• s1
• s2
• s3

Readings

• None - catch up on previous reading or svn tutorial material.

Background / Reference

• The Intel IA32 Developer Manuals, Volume 1: http://www.intel.com/products/processor/manuals/
  • Section 2.1 (skim this)
  • Section 2.2 (paying particular attention to the description of the pipelined microarchitecture)
  • Chapter 3 (paying particular attention to 3.1 (and Figure 3-1), 3.2, 3.3, 3.4)
• The Intel IA32 Developer Manuals, Volume 3A: http://www.intel.com/products/processor/manuals/
  • Chapter 2 (paying special attention to Figure 2-1, Section 2.2, Figure 2-3, and Section 9.1)